New to the Open Compute Project? Watch “OCP 101: How to Participate in the Open Compute Project” to learn how the community works — and join our mailing list, linked in the 101 video, to stay involved: This...
Dan Biederman Principal Technologist - Eridu AI As the number of ports in the switch increase substantially, it introduces novel and interesting time-related scenarios. This paper will discuss some aspects of these scenarios to share some of the finding....
Thomas Ng Platform Architect - Intel Jason Rock Distinguished Member of Technical Staff - Dell Technologies OCP NIC 3.0 continues to advance to meet next-generation bandwidth, manageability, and thermal requirements for AI-HPC platforms. This update adds PCIe Gen 7 support,...
Peter Corbett Fellow - Dell Technologies Kirankumar Bhusanurmath Product Manager - Dell Technologies Too many AI deployments stall before they ever start — GPUs sit idle waiting for data, storage choices lock you in, and stitching together compute, networking, and...
Munir Ahmad Compute Architect - Lattice Semiconductor Alex Cervantes Cloud and AI Systems Architect - Intel This session presents a streaming (flash-less) boot architecture aligned with OCP initiatives to address firmware-management complexity across datacenter systems. Todays platforms span firmware across...
Presenter(s): Hancock Chang, Director, Solution Enabling Division., MiTAC James Shie, Solution Manager, MiTAC As AI infrastructure scales from standalone servers to rack- and POD-level deployments, managing compute, networking, power, and liquid cooling through open, interoperable technologies becomes increasingly critical. This session...
Krishna Sugumaran Firmware Architect - AMD Sujoy Sen Principal Engineer - Google Akkiah (Choudary) Maddukuri Principal Engineer - Microsoft Qian Wang Software Engineer - NVIDIA Balaji Vembu Hardware Systems Engineer - AI systems - Meta Scaling AI and HPC demands robust, standardized GPU...
Giri Mudusuru Principal Firmware Architect - Microsoft Tim Lewis CTO - Insyde Software Bertrand Achard Boot Services lead - Google Raj Kapoor Fellow, Chief Firmware Architect - AMD Oleg Ilyasov BIOS Core Engineer - American Megatrends (AMI) Deploying a secure platform at scale...
Time Appliances Open Discussion & Q&A
Murali Venkat Principal Engineer - Cisco Pirooz Tooyserkani Principal Engineer - Cisco Systems, Inc. This talk details hardware architecture standard for a DPU Sled, a modular form factor for a SmartSwitch. The DPU Sled introduces an OIR-able design supporting select...
Sam Dore Product Manager - Liquid Cooling - nVent Learn about nVent & AMDs development of an RDHx solution for AMD Helios™ deployments.
Ravindranath Coimbatore Kanakarajan Distinguished Engineer - Marvell Jai Kumar Distinguished Engineer - Broadcom As AI workloads impose ever-tighter SLAs on hyperscale infrastructure, operators face heterogeneous platforms with varying capabilities and distinct hardware limits. Without a principled way to discover those...
Harish Krishnamoorthy Principal Solutions Architect - NVIDIA Parvez Shaikh Software Engineer - Meta Modern AI infrastructure depends on networks that can scale to massive GPU clusters while delivering high bandwidth, low latency, fast failure recovery, and predictable operations. Metas FBOSS,...
Larry Sharp Sr. Applications Engineer - Chroma As AI rack power levels continue to increase, validating next-generation power infrastructure has become a major challenge for system developers, power architects, and data center operators. Building MW-scale validation environments requires more...
Tim Lambert Fellow / VP - Dell Technologies, Inc. Javier Lasa Platform Architect - Intel OCP MHS - DC-SCM 3.0 Update This session shows the evolution of next generation infrastructure in terms of common enablement of modular and scalable control...
John Leung Principal Engineer - Intel Mike Raineri Distinguished Member of Technical Staff - Dell Technologies OCP prescribes the remote manageability of IT platforms and OT equipment components via the OCP-defined Redfish profiles. In the last year, a baseline profile,...
Suresh Duthiraru Debug Tools Architect - Microsoft Rolf Kuehnis Strategic Technical Alliance Manager - Lauterbach Inc. Modern data centers struggle with debug at scale traditional JTAG and probe-based approaches require physical access, lack security controls, and cannot meet hyperscale operational...
New to the Open Compute Project? Watch “OCP 101: How to Participate in the Open Compute Project” to learn how the community works — and join our mailing list, linked in the 101 video, to stay involved: The...
Jonah Hill Xanadu - Xanadu
Bijan Nowroozi Head of Ecosystem Development - Lightmatter Morris Repeta Director, Advanced Hardware Technologies, Office of the CTO - Dell Next gen AI systems require extreme throughput thus bringing silicon photonics into OCP server platforms. This shift affects escape geometry,...
Xiling Sun Principal firmware engineer - Microsoft Roksana Golizadeh Mojarad Principal Security Architect - Microsoft Todays platform attestation over Redfish is disaggregated. Attesting a server takes N transactions and N signed responses, with no platform-level artifact binding them. There is...
Theodros Yigzaw Memory System Architect - NVIDIA Vilas Sridharan RAS Architect - AMD Janusz Jurski architect - Intel Shubhada Pugaonkar Server RAS Architect - NVIDIA Samer El-Haj-Mahmoud Distinguished Engineer and System Architect - Arm As a collaboration of the whos who of contemporary...
Avinash Natarajan Senior Principal, Design Engineering - Celestica Navinsennivel Nallasivam Staff Engineer - Celestica Open Rack Management Controller–Device Manager(OpenRMC-DM-DM) provides an abstraction layer to access multiple BMCs within a rack over Redfish.We extrapolate this to build a hierarchy for complex...
Presenter(s): Tamer GUDU, SMTS Silicon Design Engineer, AMD Aleksandar Jovanovic, Senior Engineering Manager, AMD The Modular Peripheral Sideband Tunneling Interface (M-PESTI) is an emerging single-wire, half-duplex protocol standardized by the Open Compute Project (OCP) for peripheral communication. As the specification evolves,...
Ahmad Byagowi Research Scientist - TBD Lukas Landgraf Software Engineer - turbalance AI infrastructure operators have many dashboards but no common evidence model linking GPU counters, host pressure, BMC power-thermal, scheduler placement, NCCL behavior, benchmarks, and clock skew. This session...
Yair Neugeboren Sr. Product Line Manager - Oscilloquartz Anil Reddy VP gLOBAL Business Development - Oscilloquartz The talk will discuss the evolution of a timecard as a resilient A-PNT custom solution. I will show how the OCP-TAP based Timecard design can...
Harsh Bhuwania Senior Firmware Engineer - Microsoft Prashant Dewan Principal Engineer - Microsoft Software Bills of Materials (SBOMs) provide build-time transparency into software composition but remain largely static, with limited operational value in hyperscale environments. Once deployed, there is no...
Paul Grimes Principal Member of Technical Staff - AMD Chitrak Gupta Architect - American Megatrends (AMI) Firmware complexity is outpacing traditional development, and nearly every engineer now uses AI assistants -- yet on open firmware, ungoverned AI is unreliable and...
Zhongxiang ZHANG CEO - Shenzhen Litratech Co. Ltd., shan che ceo - pixora llc A bit crossing an electrical packet switch pays tens of pJ per hop (SerDes, buffering, O-E-O), flat across speed generations. A bit crossing an optical...
Mohamed Awad EVP & General Manager of Cloud AI Business Unit - Arm Agentic AI is changing the unit of scale in the data center. AI is evolving from models responding to prompts into agents that reason, use tools,...
Chris Collins AVP of Product, DSP and Optical - Credo As AI fabrics scale to hundreds of thousands of GPU nodes, optical links become a key reliability bottleneck. Failures, link flaps, and limited visibility, especially at bare-metal endpoints, impact...
Gregg Shick Validation Lead - HPE, Jeff Hilland Principal Architect - Intel This presentation examines the evolution of the Auxiliary Management Controller (AMC) specification from its v1.0 baseline to the 1.1 Version. It highlights key architectural refinements, expanded capabilities...
Gerald Bode CTO - Nlevel, Florian Engel CEO - Nlevel Jaehoon Shim Ph.D. Student - Seoul National University Injae Kang Student - Seoul National University, M A Awal Lead Controls Engineer - EPC Power Corporation Jason Barmann Director, Data Center...
ZongChang Liu Secretary of the board, CIO, FII - Foxconn As AI infrastructure scales rapidly, manufacturing has become a key driver of AI Factory success. In this session, Ingrasys will showcase its fully automated production line for AI servers. By...
Patrick Caporale Distinguished Engineer - Lenovo Hemal Shah Distinguished Engineer and Architect - Broadcom OCP has been leveraging DMTF MCTP, PLDM, and NC-SI specifications for platform management communications. MCTP Base and Binding specifications have been extended to cover new capabilities...
Allan Cantle CEO - Nallasway As AI inference goes agentic, the demand for very large context - and its associated KVCache - needing to be resident in the local HBM is skyrocketing while HBM capacity is fundamentally failing to...
Quresh Bohra Staff System Architect - TE Connectivity Tony Howard Staff System Architect - TE Connectivity The increasing trends in data centers toward higher compute density and elevated rack power levels are driving more power delivery directly to the chip....
Rama Bhimanadhuni Principal Engineering lead - Microsoft Taniya Siddiqua GPU RAS Architect - Advanced Micro Devices, Inc. This session presents advances from the Hyperscale GPU and CPU OCP workstream — a hyperscaler-silicon-vendor collaboration — in two areas diagnostics standardization and...
Public call recording of RP _ Rack & Power project.
ofer yehielli Technical Lead Manager - Google, MARIUSZ ORIOL Manageability Architecture - NVIDIA Janusz Jurski architect - Intel Presentation provides an update on the developments in OBMF WS, with a particular focus on release of v1.0 of the OBMF-ICP (Interface...
David Reiner President - SPEC (Standard Performance Evaluation Corporation) The explosive growth of agentic AI and growing HPC market have elevated the server CPU to a critical element in the datacenter. At the same time, the competitive landscape is...
Presenter(s): Phillip Leech, Senior Technologist / Customer Architect, HPE Bill Scherer, Architect, HPE Munir Ahmad, Compute Architect, Lattice Semiconductor The OCP MHS Plug-and-Play (M-PNP) workstream addresses the challenges of ensuring SCM, HPM and peripheral interoperability via specifying interfaces, APIs, and data models....
Dong Wei Lead Standards Architect and Fellow - ARM Samer El-Haj-Mahmoud Distinguished Engineer and System Architect - Arm The Server Base System Architecture (SBSA) workstream establishes a common hardware architecture baseline for Arm-based servers within the OCP Server Project. The...
Jim Harford System Architect - Broadcom As data centers grow in size and complexity, it becomes even more important to manage their hardware components in an effective, efficient, and timely manner; such that data center service levels and financial...
Ajay Kamalvanshi Senior Director, GPU System Software - NVIDIA Power, not silicon, now sets the ceiling on AI factory revenue. Yet measurements across mixed production workloads — inference, training, and post-training RL — show that a large share of...
Presenter(s): Rongchun Zhou, Network Hardware Engineer, Meta Reza Niazmand, Technical Program Manager, Meta Meta IceCube is an advanced 102.4T non-blocking Ethernet switch built on the Broadcom TH6C switch ASIC and running FBOSS. In a 2OU form factor with 64× OSFP-RHS user...
Joe Skorjanec Product Line Manager DC Power - Eaton As AI infrastructure drives unprecedented rack densities, the industry is accelerating toward 800VDC power architectures to improve efficiency, simplify power distribution, and support future scaling requirements. While the benefits are...
Presenter(s): Patrick Liu, Thermal Engineer, Auras Technology Co., Ltd. Ali Heydari, Technical Director and Distinguished Engineer, Data Center Cooling & Infrastructure, NVIDIA As AI models continue to grow in scale and high-performance computing (HPC) workloads rapidly increase, the thermal design power...
Andrew Dieckmann Corporate Vice President & General Manager - AMD Steve Scott Corporate Fellow - AMD Alan Smith Corporate Fellow - AMD As AI workloads grow in complexity and scale, the rack becomes a critical frontier for system innovation. Join Andrew...
Presenter(s): Todd Rosedahl, Director -- Systems and AI Strategy, Jabil David Heinrich, Fellow, HPE Chitrak Gupta, Architect, American Megatrends (AMI) The MHS Plug-and-Play (M-PNP) workstream addresses the challenges of ensuring Secure Control Module (SCM), Host Processor Module (HPM) and peripheral interoperability by...
Wil Myrick Chief Technologist - ENSCO ENSCO presents an Open Time Server Cluster (OTS-C) architecture for creating resilient timing servers at the edge combining open source timing software and inexpensive commercial-off-the-shelf (COTS) hardware. The architecture leverages open-source timing software...